Semiconductor Manufacturing: The Rising Cost of DUV Workarounds
Chinese foundries use multiple patterning to bypass EUV bans, but the method reduces yields and increases production expenses.
By Harper Laurent ·
Chinese chipmakers are producing advanced silicon using deep ultraviolet lithography despite export controls that block access to extreme ultraviolet machines from ASML. The strategy relies on exposing critical layers of the chip multiple times to achieve the necessary density. While this method allows manufacturers like SMIC and CXMT to continue production, it introduces higher costs and technical challenges.
ASML is the sole producer of EUV equipment, which uses 13.5 nanometer wavelength light to print fine features. Analysts estimate the capability gap between China and Western rivals is at least five years. SMIC demonstrated its ability to bypass this limitation by creating the Kirin 9000S processor for the Huawei Mate 60 Pro in 2023. That chip used a second-generation 7 nanometer class process without EUV. More recent analysis suggests SMIC has advanced its DUV-based process to densities approaching 5 nanometer levels, though it still lags behind TSMC and Samsung.
The technical method involves multiple patterning, where designers split a complex layer into several simpler patterns. Chris Mack, co-founder and CTO of Fractilia, noted that industry standards previously suggested three exposures on a 193 immersion tool cost the same as one EUV exposure. However, at four masks, EUV becomes the more economical choice. Each additional pattern requires precise alignment with previous layers. This process accumulates overlay errors and process variation, forcing designers to add extra space around features. That extra space enlarges the chip and reduces the number of usable dies per wafer, which can cost tens of thousands of dollars.
Memory production illustrates the efficiency loss. Morgan Stanley reported in June that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as Western competitors. The bank described lithography access as a hard ceiling for Chinese memory development. Mack emphasized that node labels like 5 nanometer or 3 nanometer have limited meaning without context. He stated that SMIC’s N+3 process, while a step forward, remains less scaled than established 5 nanometer processes from Samsung and TSMC.
DUV technology still has potential for expansion. Micron developed its 1-alpha DRAM without EUV by using multiple patterning and tight process control. Mack said Micron pushed 193 nanometer technology farther than other memory makers. Morgan Stanley believes CXMT’s planned move to 1-alpha DRAM for HBM3e is achievable without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow firms to use DUV for the latest DRAM generations by the end of the decade. Mack added that China could make significant progress with a full 193 immersion ecosystem, though he noted memory is easier to produce than logic chips.
Micron eventually adopted EUV for its 1-gamma DRAM, which offers more than 30 percent greater bit density per wafer than the previous 1-beta generation. EUV has its own issues, such as stochastic effects that require higher exposure doses and increased costs. Mack said he would be hard pressed to believe a 3 nanometer or 2 nanometer node could be economically viable without EUV.
Chinese manufacturers will continue to push DUV limits while accepting trade-offs such as larger dies, lower yields, and longer manufacturing times. Morgan Stanley assumes CXMT will stay on 1-alpha without EUV but increase its share of global DRAM bit supply from 14 percent in 2026 to 16 percent in 2028 through new capacity. The bank also projects that China’s AI chip self-sufficiency will rise from 42 percent in 2025 to 70 percent by 2030, with persistent gaps remaining in EUV, HBM, and advanced software.
